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10 commonly used chip packaging technologies

2021-12-15 14:01:05 246

1. The ratio of chip area to package area improves the package efficiency, which is as close as possible to 1: 1;


2. The pins should be as short as possible to reduce the delay, and the distance between pins should be as far as possible to ensure mutual non-interference and improve the performance;


3. Based on the requirement of heat dissipation, the thinner the package, the better.

Packaging is mainly divided into DIP dual in-line and SMD chip packaging. In terms of structure, the package has experienced the development of early transistor TO (such as TO-89 and TO92) package to dual in-line package, then SOP small outline package was developed by PHILIP Company, and SOJ(J-shaped pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (reduced SOP) and TSSOP (small outline package) were gradually derived. From the aspect of materials and media, including metals, ceramics and plastics, many circuits requiring high-strength working conditions, such as military and aerospace, still have a large number of metal packages.


1. BGA package (ball grid array)

Spherical contact display, one of surface mount packages. On the back of the printed substrate, spherical bumps are made to replace pins according to the display method, LSI chips are assembled on the front of the printed substrate, and then sealed by molding resin or potting method. Also known as convex display carrier (PAC). The pins can exceed 200, which is a package for multi-pin LSI. The package body can also be made smaller than QFP (quad flat package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; While the 304-pin QFP with a pin center distance of 0.5mm is 40mm square. Moreover, BGA does not need to worry about the pin deformation like QFP. This package was developed by Motorola Company of the United States. It was first used in portable phones and other devices, and it will be widely used in personal computers in the United States in the future. At first, the center distance of BGA pins (bumps) is 1.5mm, and the number of pins is 225. Now some LSI manufacturers are developing 500-pin BGA. BGA's problem is the appearance inspection after reflow soldering. It is not clear whether it is an effective visual inspection method. Some people think that the connection can be regarded as stable because of the large center distance of welding, and it can only be handled by functional inspection. Motorola Company of the United States called the package sealed by molding resin OMPAC, while the package sealed by potting method was called GPAC (see OMPAC and GPAC).


2. BQFP package (quad flat packagewith bumper)

Four-side pin flat package with buffer pad. One of QFP packages, the four corners of the package body are provided with protrusions (cushion pads) to prevent the pins from bending and deformation during transportation. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASIC. The center-to-center distance is 0.635mm, and the number of pins ranges from 84 to 196 (see QFP).


3. butt joint pin grid array

Another name for surface mount PGA (see surface mount PGA).


4. C-(ceramic) package

Symbol for ceramic package. For example, CDIP stands for ceramic DIP. Is a sign that is often used in practice.


5. Cerdip package

Ceramic dual in-line package sealed with glass is used in ECL RAM, DSP (Digital Signal Processor) and other circuits. Cerdip with glass window

Used for ultraviolet erasing EPROM and microcomputer circuit with EPROM inside, etc. The pin center distance is 2.54mm, and the number of pins ranges from 8 to 42. In Japan, this package is called DIP-G(G (G means glass sealing).


6. Cerquad package

One of the surface mount packages, namely ceramic QFP with lower sealing, is used to package logic LSI circuits such as DSP. Cerquad with windows are used to package EPROM circuits. Heat dissipation is better than plastic QFP, and it can tolerate 1. 5 ~ 2w power under natural air cooling. But the packaging cost is higher than that of plastic.

QFP is 3 ~ 5 times higher. There are various specifications such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, etc .. The number of pins is from 32 to 368.

Ceramic chip carrier with pins, one of surface mount packages, leads from four sides of the package in a T-shape. Windows are used to package ultraviolet erasing EPROM and microcomputer circuit with EPROM. This package is also called QFJ, QFJ-G (see QFJ).


7. CLCC package (ceramic leadedchip carrier)

Ceramic chip carrier with pins, one of surface mount packages, leads from four sides of the package in a T-shape. Windows are used to package ultraviolet erasing EPROM and microcomputer circuit with EPROM. This package is also called QFJ, QFJ-G (see QFJ).


8. COB package (chip on board)

Chip on board packaging is one of bare chip mounting technologies. Semiconductor chips are hand-over mounted on printed circuit boards. The electrical connection between chips and substrates is realized by wire stitching, and the electrical connection between chips and substrates is realized by wire stitching, which is covered with resin to ensure the reliability. Although COB is a simple bare chip mounting technology, its packaging density is far less than that of TAB and flip chip bonding technology.


9、DFP(dual flat package)

Pin flat package on both sides. It is another name for SOP (see SOP). There used to be this term, but now it is basically not used.


10、DIC(dual in-line ceramic package)

Another name for ceramic DIP (including glass seal) (see dip).